A Versatile FPGA-based High Speed Bit Error Rate Testing Scheme
نویسنده
چکیده
.......................................................................................................... i Résumé ........................................................................................................... ii Acknowledgments ........................................................................................ iii Table of
منابع مشابه
High-speed All- Optical Time Division Multiplexed Node
In future high-speed self-routing photonic networks based on all-optical time division multiplexing (OTDM) it is highly desirable to carry out packet switching, clock recovery and demultplexing in the optical domain in order to avoid the bottleneck due to the optoelectronics conversion. In this paper we propose a self-routing OTDM node structure composed of an all-optical router and demultiplex...
متن کاملFPGA Implementation of JPEG and JPEG2000-Based Dynamic Partial Reconfiguration on SOC for Remote Sensing Satellite On-Board Processing
This paper presents the design procedure and implementation results of a proposed hardware which performs different satellite Image compressions using FPGA Xilinx board. First, the method is described and then VHDL code is written and synthesized by ISE software of Xilinx Company. The results show that it is easy and useful to design, develop and implement the hardware image compressor using ne...
متن کاملHigh-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers
We develop a custom Bit Error Rate test bench based on Altera’s Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial stand alone tester. The 8B/10B protocol is implemented and its effects studied. A variable optical attenuator is inserted in the fibre loop to induce transmissi...
متن کاملDesign of Arrayed Waveguide Grating based Optical Switch for High Speed Optical Networks
This paper demonstrates the design of an Arrayed Waveguide Gratings (AWG) based optical switch. In the design both physical and network layer analysis is performed. The physical layer power and noise analysis is done to obtain Bit Error Rate (BER). This has been found that at the higher bit rates, BER is not affected with number of buffer modules. Network layer analysis is done to obtain perfor...
متن کاملAn FPGA Design of Generalized Low-density Parity-check Codes for Rate-adaptive Optical Transport Networks
Forward error correction (FEC) is as one of the key technologies enabling the next-generation high-speed fiber optical communications. In this paper, we propose a rate-adaptive scheme using a class of generalized low-density parity-check (GLDPC) codes with a Hamming code as local code. We show that with the proposed unified GLDPC decoder architecture, a variable net coding gains (NCGs) can be a...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2003